In these years, as computer systems have become widely used, needs for technique of efficiently performing processing of multimedia data including audio, video, and the like have been growing. Multimedia processing is a repeat of simple data transfers, which is required to have high real-time property and throughput. Thus, the direct memory access system (DMA system) has been employed for the multimedia processing instead of the program I/O control system (PIO control system) which places a large load on a CPU.
In a conventional computer system having a CPU, a memory, an input device, an output device, and a DMA controller, in the case of achieving periodic high-speed transfers of multimedia data between the input device and the memory, among different areas in a memory, and between the memory and the output device, interrupt program has been executed by periodic interrupts from a timer to the CPU to control operation of the DMA controller by this interrupt program.
Also, if it is unable to measure the timing by the timer, the polling method, which continues reading a register value indicating states of peripheral devices by the CPU until the peripheral devices become a suitable state for starting DMA transfers, has been employed.
Further, as the DMA controller disclosed in Japanese Patent Application Laid-Open Publication No. H8-249267 (Patent Document 1), if a control cycle of the DMA controller is accurate, a method, which reduces the CPU load for interrupt by measuring time by a counter embedded in the DMA controller and performing DMA transfers in a constant cycle without interposing a CPU, has been employed.
However, if jitter exists in the operation cycle of the peripheral devices, it has been unable to employ the method such as that of Patent Document 1, and it has been required to employ interrupt or the polling method as described above.    Patent Document 1: Japanese Patent Application Laid-Open Publication No. H8-249267